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Silicon Labs /SiM3_NRND /SIM3U166_B /SPI_2 /CLKRATE

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Interpret as CLKRATE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV

Description

Module Clock Rate Control

Fields

CLKDIV

Clock Divider.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data